In order to realize a D/A converter on a CMOS device, general use is made of a voltage-scaling type D/A converter in which a plurality of resistors for dividing a voltage are connected in series between two reference voltages, and a divided voltage corresponding to input digital data is selected and output. However, this converter has difficulty in the fact that, in a high bit, variation in the value of resistance deteriorates integral linearity.
In contrast, use is made of a charge-scaling type D/A converter in which a divided voltage between two reference voltages is output by use of a plurality of binary-weighted capacitors whose capacitance values have a ratio of, for example, 1:2:4 making use of the greatness in the ratio precision of capacitance values in a CMOS device. This principle is described, for example, in “Bipolar and MOS Analog Integrated Circuit Design” written by Alan B. Grebene and states that this type has an advantage in a CMOS circuit.
A 4-bit D/A converter embodied on the basis of this principle is shown in FIG. 15, and the operation of the converter will be described with reference to the figure. In FIG. 15, capacitors C1 to C4 are binary-weighted capacitors having the ratio of 1:2:4:8, and a capacitor C0 is a terminating capacitor used to make the sum of capacitance values equal to 16(=24). An end of each of these capacitors is connected to a voltage node N1 in common, and the voltage of this node N1 is connected to an output terminal Vout through a buffer amplifier (AMP). The other ends of the capacitors C0 to C4 are connected to switches SWR0 to SWR4, respectively. Since the switches SWR0 to SWR4 reach a state shown in FIG. 15 in a reset operation, and a switch SWR5 shorts both ends of each capacitor, an electric charge is reset at 0. The electric potential of the node N1 is given by a bias voltage Vb when reset. After the reset operation is performed, the switch SWR5 is turned off, and the switches SWR0 to SWR4 are connected to the side opposite to the state shown in FIG. 15 when an output operation is performed to output a D/A conversion voltage. The independent terminal side of each capacitor is selectively connected to either GND or reference voltage Vref through switches SWD1 to SWD4 controlled by digital data. At this time, only the independent terminal side of the capacitor C0 is fixed to be always connected to GND.
In the thus formed structure and operation, the total electric charges stored in the capacitors in the reset operation and those stored in the output operation are constant according to the law of conservation of charge, and therefore Equation (1) is established wherein Vo is the voltage of the node N1 in the output operation. In Equation (1), V1 to V4 are voltage values at which the independent terminal sides of the capacitors are connected according to digital data, and they are each 0 or Vref.Vo*C0+(Vo−V1)*C1+(Vo−V2)*C2+(Vo−V3)*C3+(Vo−V4)*C4=0  (1)
In Equation (1), since Vi (i=1,2,3,4) is controlled by digital data and is either 0 or Vref, Vi can be expressed as Vi=Di*Vref on the supposition that if Di=0, a connection to GND is established (having a value of 0), and, if Di=1, the value becomes equal to Vref wherein Di (i=1,2.3,4) is digital data of each bit. Further, since the capacitor ratio has the relation C0:C1:C2:C3:C4=1:1:2:4:8, voltage Vo is expressed as in Equation (2) by solving Equation (1) under standardization using C0. In Equation (2), D1 to D4 are digital data of each bit, and the values of these are each 1 or 0.Vo=Vref*(D1+2*D2+4*D3+8*D4)/16  (2)
According to Equation (2), it is understood that the output of Vout has arbitrary analog voltages from 0 to 15/16Vref in Vref/16 step depending on the method of providing the digital data D1 to D4. If binary-weighted capacitors in which weighting is performed in the ratio of, for example, 1:2:4: . . . :2n−1 are prepared for n bits, and if a capacitor whose ratio is 1 is added as a terminating capacitor, a n-bit D/A converter can be realized as well as the above. At this time, it is understood that 2n unit capacitors are required to realize the n-bit D/A converter under the assumption that the smallest capacitor is a unit capacitor. The voltage applied to the capacitor in the output operation is either GND or Vref in FIG. 15, but, if they are set as two arbitrary reference voltages, output to divide the two reference voltages can be obtained.
Since the capacitor can have higher ratio precision than the resistor on the CMOS device, the charge-scaling type D/A converter shown in FIG. 15 is fundamentally advantageous. However, since the input capacitance of a buffer and the parasitic capacitance Cp by the switch SWR5 exist in the node N1 of FIG. 15 in practice, an electric charge is distributed to this parasitic capacitance, and, as a result, an error occurs. If the voltage of the node N1 is Vb by a bias voltage source in Equation (1) in the reset operation, Equation (1) can be rewritten like Equation (3) in consideration of the electric charge of the parasitic capacitance. Herein, Q is the total electric charge held besides the parasitic capacitance in the output operation in the left term in Equation (1) as shown in Equation (4).Q+Vo*Cp=Vb*Cp  (3)Q=Vo*C0+(Vo−X1)*C1+(Vo−X2)*C2+(Vo−X3)*C3+(Vo−X4)*C4  (4)
Therefore, as is understood by solving Equation (3) on the assumption that Cp has no voltage dependence, one step of the D/A conversion output decreases to Vref/(16+Cp/C0) because of the influence of the term of the parasitic capacitance Cp shown in Equation (3), and, disadvantageously, an intended output range cannot be obtained. If the parasitic capacitance Cp has voltage dependence, the linearity of the D/A conversion output will also deteriorate. Therefore, the unit capacitor C0 must be enlarged to relatively lessen the influence of the parasitic capacitance. However, this has a problem in that an area occupied by the D/A converter becomes large.
On the other hand, as is understood from Equation (3), the right and left terms of the parasitic capacitance Cp will be canceled, and no error will occur if the voltage Vb of the node N1 in the reset operation is equal to the output voltage Vo. Therefore, Japanese Patent No. 3166603 discloses a method in which, in order to give a voltage nearing the voltage Vo output by the D/A converter as Vb in the reset operation, the output once subjected to the D/A conversion is held by a sample-hold circuit provided behind the buffer of FIG. 15, and its output is given as Vb when second resetting is performed. However, since this method requires a plurality of reset operations to obtain one D/A conversion output, this method is disadvantageous in raising a converting rate. Additionally, the aforementioned conventional methods have a problem in that an offset error caused by the offset voltage of the buffer also occurs in the D/A converter output.
As other background art, “A Multibit Delta Sigma Audio DAC with 120-dB Dynamic Range” (Ichiro Fujimori et. al, IEEE JOURNAL OF SOLID-STATE CIRCUITS VOL.35, NO.8, AUGUST 2000, P.1066) discloses a five-bit SC DAC with hybrid post filter in FIG. 8. However, this Circuit is different type from the above DAC.